- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
- Low power, high throughput network-on-chip fabric for 3D multicore processors
- On old and new routing problems
A Test Synthesis Approach To Reducing Ballast Dft Overhead
| Title | A Test Synthesis Approach To Reducing Ballast Dft Overhead |
| Publication Type | Conference Paper |
| Year of Publication | 1997 |
| Authors | Chang, D, Lee, T-C, Marek-Sadowska, M, Aikyo, T, Cheng, K-T |
| Conference Name | Design Automation Conference, 1997. Proceedings of the 34th |
| Date Published | jun |
| Abstract | Not available |
| DOI | 10.1109/DAC.1997.597193 |
