- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
A Test Synthesis Approach To Reducing Ballast Dft Overhead
| Title | A Test Synthesis Approach To Reducing Ballast Dft Overhead |
| Publication Type | Conference Paper |
| Year of Publication | 1997 |
| Authors | Chang, D, Lee, T-C, Marek-Sadowska, M, Aikyo, T, Cheng, K-T |
| Conference Name | Design Automation Conference, 1997. Proceedings of the 34th |
| Date Published | jun |
| Abstract | Not available |
| DOI | 10.1109/DAC.1997.597193 |
