Minimal Delay Interconnect Design Using Alphabetic Trees

TitleMinimal Delay Interconnect Design Using Alphabetic Trees
Publication TypeConference Paper
Year of Publication1994
AuthorsVittal, A, Marek-Sadowska, M
Conference NameDesign Automation, 1994. 31st Conference on
Date Publishedjune
AbstractWe propose a new algorithm for the performance-driven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner and does not greedily add edges as in conventional approaches. The algorithm can handle cases where the sink capacitances are different. Good results are obtained while running two to sixty times faster than three existing algorithms on practical instances.