Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

TitleTwin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
Publication TypeConference Paper
Year of Publication2011
AuthorsMaly, W, Singh, N, Chen, Z, Shen, N, Li, X, Pfitzner, A, Kasprowicz, D, Kuzmicz, W, Yi-Wei Lin, Marek-Sadowska, M
Conference NameMixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Date Publishedjune
Keywords3D integration, 3D junctionless VeSFET, electrical property, highly periodic layout, integrated circuit layout, MOS integrated circuits, MOSFET, three-dimensional integrated circuits, twin gate vertical slit FET, vertical slit device architecture, vertical slit transistor based integrated circuit
AbstractThis paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs) [2,3]. This paper discusses the basic idea of vertical slit device architecture, the physics of VeSFETs, their key electrical properties in comparison with trigate FinFETs, and shows experimental characteristics of fabricated devices.