Floorplanning with pin assignment

TitleFloorplanning with pin assignment
Publication TypeConference Paper
Year of Publication1990
AuthorsPedram, M, Marek-Sadowska, M, Kuh, ES
Conference NameComputer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Date Publishednov
Keywordscircuit layout CAD, floorplanning, general cell layouts, hierarchical technique, interconnection, layout aspect ratio, pin assignment, positions, shapes, upper bound delay constraints, user specified constraints, Xerox general cell benchmark
AbstractA hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for a Xerox general cell benchmark are reported