| Title | Timing driven placement |
| Publication Type | Conference Paper |
| Year of Publication | 1989 |
| Authors | Marek-Sadowska, M, Lin, S |
| Conference Name | Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on |
| Date Published | nov |
| Keywords | algorithms, chip, circuit layout CAD, graph models, graph theory, improved performance, integrated circuits, logic CAD, minimize, physical design, placement programs, sea-of-gates designs, summation of wire lengths, timing constraints, timing driven placement |
| Abstract | The authors address the problem of incorporating timing constraints into the physical design of integrated circuits. First they formulate the problem and discuss graph models suitable for its analysis. Next, they describe algorithms resulting in placements of improved performance in comparison to placements whose objective is to minimize the summation of wire lengths on the chip. Finally, the authors show preliminary results of their placement programs for the sea-of-gates designs |
| DOI | 10.1109/ICCAD.1989.76912 |
