Low power, high throughput network-on-chip fabric for 3D multicore processors

TitleLow power, high throughput network-on-chip fabric for 3D multicore processors
Publication TypeConference Paper
Year of Publication2011
AuthorsNandakumar, VS, Marek-Sadowska, M
Conference NameComputer Design (ICCD), 2011 IEEE 29th International Conference on
Date Publishedoct.
Keywords3D multicore processor, 3D network-on-chip architecture, cache block, CMOS integrated circuits, CMOS technology, energy consumption, heterogeneous 3D chip, integrated circuit design, long wires, multiprocessing systems, network parameter, network-on-chip, NoC communication fabric, processor cores, VeSFET technology
AbstractLong wires degrade significantly the performance of network-on-chip (NoC) communication fabric in large multicore processors. 3D network-on-chip architecture alleviates the problem of long wires, but practical limitations of CMOS technology restrict such structures to two active layers only. In this work, we study a heterogeneous 3D chip with processor cores and cache blocks implemented in CMOS and NoC fabric in VeSFET technology. Such a 3D architecture shows significant improvements in all network parameters including latency, power and energy consumption compared to existing 3D NoCs.
DOI10.1109/ICCD.2011.6081458