- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Performance Optimization Using Variable-Latency Design Style
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
- Low power, high throughput network-on-chip fabric for 3D multicore processors
Wire length prediction-based technology mapping and fanout optimization
| Title | Wire length prediction-based technology mapping and fanout optimization |
| Publication Type | Conference Paper |
| Year of Publication | 2005 |
| Authors | Liu, Q, Marek-Sadowska, M |
| Conference Name | ISPD '05: Proceedings of the 2005 international symposium on Physical design |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 1-59593-021-3 |
| DOI | 10.1145/1055137.1055167 |
