- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Performance Optimization Using Variable-Latency Design Style
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
- Low power, high throughput network-on-chip fabric for 3D multicore processors
Closed-Form Crosstalk Noise Delay Metrics
| Title | Closed-Form Crosstalk Noise Delay Metrics |
| Publication Type | Journal Article |
| Year of Publication | 2003 |
| Authors | Chen, LH, Marek-Sadowska, M |
| Journal | Analog Integr. Circuits Signal Process. |
| Volume | 35 |
| Pagination | 143–156 |
| ISSN | 0925-1030 |
| DOI | 10.1023/A:1024126531872 |
