- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Performance Optimization Using Variable-Latency Design Style
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
- Low power, high throughput network-on-chip fabric for 3D multicore processors
Efficient circuit clustering for area and power reduction in FPGAs
| Title | Efficient circuit clustering for area and power reduction in FPGAs |
| Publication Type | Journal Article |
| Year of Publication | 2002 |
| Authors | Singh, A, Parthasarathy, G, Marek-Sadowska, M |
| Journal | ACM Trans. Des. Autom. Electron. Syst. |
| Volume | 7 |
| Pagination | 643–663 |
| ISSN | 1084-4309 |
| DOI | 10.1145/605440.605448 |
