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Recent Papers

  • Vertical Slit Field Effect Transistor in ultra-low power applications
  • Can pin access limit the footprint scaling?
  • A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
  • Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
  • Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
  • Low power, high throughput network-on-chip fabric for 3D multicore processors
  • Rapid layout pattern classification
More...

Efficient circuit clustering for area and power reduction in FPGAs

TitleEfficient circuit clustering for area and power reduction in FPGAs
Publication TypeJournal Article
Year of Publication2002
AuthorsSingh, A, Parthasarathy, G, Marek-Sadowska, M
JournalACM Trans. Des. Autom. Electron. Syst.
Volume7
Pagination643–663
ISSN1084-4309
DOI10.1145/605440.605448
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Electrical and Computer Engineering, Harold Frank Hall, University of California, Santa Barbara, CA - 93106.

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