- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
- Low power, high throughput network-on-chip fabric for 3D multicore processors
- Rapid layout pattern classification
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
| Title | Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs |
| Publication Type | Conference Paper |
| Year of Publication | 1997 |
| Authors | Chang, D, Marek-Sadowska, M |
| Conference Name | FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 0-89791-801-0 |
| DOI | 10.1145/258305.258331 |
