Improving the Resolution of Single-Delay-Fault Diagnosis

TitleImproving the Resolution of Single-Delay-Fault Diagnosis
Publication TypeJournal Article
Year of Publication2008
AuthorsMehta, V, Marek-Sadowska, M, Tsai, K-H, Rajski, J
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination932 -945
Date Publishedmay
Keywordsautomatic test pattern generation, delay fault identification, design-timing failures, failure log processing, fault location, manufacturing defects, nonrobust test patterns, parameter variations, passing patterns, single-delay-fault diagnosis, timing-aware automatic test pattern generation sets
AbstractWith feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to performing delay-fault diagnosis for robust and nonrobust tests. We enhance the diagnostic resolution by utilizing passing patterns, processing failure logs at various slower frequencies, and applying n-detection and timing-aware automatic test pattern generation sets. Experimental results show that our approach can diagnose delay faults with good resolution. The algorithm is stable with respect to delay variations that manufactured chips might experience.