- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
- Performance Optimization Using Variable-Latency Design Style
- Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
Switch box routing: a retrospective
| Title | Switch box routing: a retrospective |
| Publication Type | Journal Article |
| Year of Publication | 1992 |
| Authors | Marek-Sadowska, M |
| Journal | Integr. VLSI J. |
| Volume | 13 |
| Pagination | 39–65 |
| ISSN | 0167-9260 |
| DOI | 10.1016/0167-9260(92)90017-S |
