| Title | Timing-Aware Multiple-Delay-Fault Diagnosis |
| Publication Type | Conference Paper |
| Year of Publication | 2008 |
| Authors | Mehta, V, Marek-Sadowska, M, Tsai, K-H, Rajski, J |
| Conference Name | Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on |
| Date Published | march |
| Keywords | automatic test pattern generation, delay variation, design timing, diagnosis algorithm, fault simulation, integrated circuit testing, timing, timing-aware multiple-delay-fault diagnosis |
| Abstract | With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that these errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay fault diagnosis problem and propose a novel, simulation-based approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower- than-nominal clock frequencies. We experimentally determined our diagnosis algorithm s sensitivity to delay variations. |
| DOI | 10.1109/ISQED.2008.4479734 |
