Timing analysis considering IR drop waveforms in power gating designs

TitleTiming analysis considering IR drop waveforms in power gating designs
Publication TypeConference Paper
Year of Publication2008
AuthorsWeng, S-H, Kuo, Y-M, Chang, S-C, Marek-Sadowska, M
Conference NameComputer Design, 2008. ICCD 2008. IEEE International Conference on
Date Publishedoct.
Keywordsgate delay calculation, integrated circuit design, integrated circuit noise, IR drop noise, IR drop waveforms, linear programming, linear programming approach, power gating designs, sleep transistors, timing, timing analysis, virtual voltage level, VLSI, VLSI design process
AbstractIR drop noise has become a critical issue in advanced process technologies. Traditionally, timing analysis in which the IR drop noise is considered assumes a worst-case IR drop for each gate; however, using this assumption provides unduly pessimistic results. In this paper, we describe a timing analysis approach for power gating designs. To improve the accuracy of the gate delay calculation we determine the virtual voltage level by taking into account the IR drop waveforms across the sleep transistors. These can be obtained efficiently using a linear programming approach. Our experimental results are very promising.