| Title | Is there always performance overhead for regular fabric? |
| Publication Type | Conference Paper |
| Year of Publication | 2008 |
| Authors | Yi-Wei Lin, Marek-Sadowska, M, Maly, W, Pfitzner, A, Kasprowicz, D |
| Conference Name | Computer Design, 2008. ICCD 2008. IEEE International Conference on |
| Date Published | oct. |
| Keywords | 3-D geometry transistor, chip manufacturability, field effect transistor circuits, high-density transistor arrays, integrated circuit fabrication, integrated circuit interconnections, integrated circuit layout, integrated circuit manufacture, OPC-free interconnect manufacturing process, optical proximity correction, photo-lithographiy, photolithography, power density, proximity effect (lithography), super-regular layout style, vertical slit field effect transistor circuits, VeSFET |
| Abstract | In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area. |
| DOI | 10.1109/ICCD.2008.4751916 |
