ECO-Map: Technology remapping for post-mask ECO using simulated annealing

TitleECO-Map: Technology remapping for post-mask ECO using simulated annealing
Publication TypeConference Paper
Year of Publication2008
AuthorsModi, N, Marek-Sadowska, M
Conference NameComputer Design, 2008. ICCD 2008. IEEE International Conference on
Date Publishedoct.
KeywordsBoolean cover, Boolean functions, ECO-Map, engineering change orders, integrated circuit design, masks, metal masks, simulated annealing, spare-recycled cells, technology remapping, transistor mask, VLSI
AbstractWith transistor mask costs soaring and the delays associated with full design re-spins escalating, post-mask Engineering Change Orders (ECOs) - design changes after the masks have been prepared - are increasingly carried out by keeping transistor masks intact and revising only the metal masks. In this paper, we propose a novel design flow for achieving technology remapping for post-mask ECOs. In contrast to conventional technology mapping and placement algorithms that have no notion of the quantity for each gate type and the location of placed spare/recycled cells, our flow ECO-Map provides an ideal scalable framework for achieving global optimization in a post-mask ECO scenario. Given the changed logic due to a functional ECO and a limited number of placed spare/recycled cells, ECO-Map finds a resource-feasible Boolean cover and optimally fits the changed logic into the available resources. This ensures minimal perturbation of the existing solution and keeps transistor masks intact, thus reducing non-recurring engineering (NRE) costs. Experiments performed on MCNC benchmarks show the effectiveness of our approach.