| Title | A study of netlist structure and placement efficiency |
| Publication Type | Journal Article |
| Year of Publication | 2005 |
| Authors | Liu, Q, Marek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 24 |
| Pagination | 762 - 772 |
| Date Published | may |
| ISSN | 0278-0070 |
| Keywords | analytic placement, circuit complexity, circuit layout, circuit stability, interconnection complexity, interconnections, netlist structure, partition based placement, placement efficiency, placement stability, simulated annealing, simulated annealing based placement |
| Abstract | In this paper, we examine the relationship between netlist structure and the efficiency of placers measured in terms of quality and stability of results. We analyze three types of placers: analytic, simulated-annealing based, and partition based. We have tested these placers on industrial and synthetic benchmarks. Based on our observations and analyzes of experimental results, we draw several useful conclusions: 1) Various placers favor netlists with different structural characteristics; 2) placement efficiency correlates with interconnection complexity of the circuits; 3) global nets increase the effort to eliminate overlaps of cells and degrade the efficiency of analytic placers; and 4) global nets can improve placement stability of partition-based placers. |
| DOI | 10.1109/TCAD.2005.846364 |
