Benefits and costs of power-gating technique

TitleBenefits and costs of power-gating technique
Publication TypeConference Paper
Year of Publication2005
AuthorsJiang, H, Marek-Sadowska, M, Nassif, SR
Conference Name2005 IEEE International Conference on Computer Design
Date Publishedoct.
Keywordsdecap area, integrated circuit design, leakage currents, leakage power saving, low-power electronics, phase locked loops, power mesh granularity, power-gating technique, sleep-transistor size, supply voltage level, transistors, voltage regulators
AbstractPower-gating is a technique for saving leakage power by shutting off the idle blocks. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and may make the technique not worth the effort. In this paper, we report on our study of the benefits and costs of the power-gating technique in terms of power, area, and performance. We model and analyze several strongly related parameters such as sleep-transistor size, decap area, and supply voltage level. We also report on our experiments to demonstrate how the gated area, circuit behavior and power mesh granularity affect the power gating technique at the system level. Experimental results show that, by compromising 4% of the total area and 5% of the dynamic power, we can achieve 47% leakage power saving while maintaining the same performance. With technology scaling down, the saving is significant. We conclude that we can benefit from the power-gating technique in future technology nodes.