- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Buffer sizing for clock power minimization subject to general skew constraints
| Title | Buffer sizing for clock power minimization subject to general skew constraints |
| Publication Type | Conference Paper |
| Year of Publication | 2004 |
| Authors | Wang, K, Marek-Sadowska, M |
| Conference Name | Design Automation Conference, 2004. Proceedings. 41st |
| Date Published | july |
| Abstract | Not available |
