| Title | Eliminating false positives in crosstalk noise analysis |
| Publication Type | Conference Paper |
| Year of Publication | 2004 |
| Authors | Ran, Y, Kondratyev, A, Watanabe, Y, Marek-Sadowska, M |
| Conference Name | Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings |
| Date Published | feb. |
| Keywords | Boolean formulation, Boolean functions, Boolean logic, circuit operation, crosstalk, crosstalk noise analysis method, delays, gate delays, interference suppression, minmax delay model, noise elimination, noise faults, path delay, signal transitions, timing |
| Abstract | Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accurate analysis requires a careful examination of timing and functional properties of the circuit. This paper proposes a method to check the "true" noise impact on path delay. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The proposed technique is scalable as it keeps the size of Boolean formulation linear to the size of the modeled circuit. By applying it to a set of large circuits, it has eliminated up to 50% of noise delay faults reported by conventional noise analysis method. |
| DOI | 10.1109/DATE.2004.1269054 |
