- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Low power, high throughput network-on-chip fabric for 3D multicore processors
- Rapid layout pattern classification
- Variation-aware electromigration analysis of power/ground networks
Pre-layout wire length and congestion estimation
| Title | Pre-layout wire length and congestion estimation |
| Publication Type | Conference Paper |
| Year of Publication | 2004 |
| Authors | Liu, Q, Marek-Sadowska, M |
| Conference Name | Design Automation Conference, 2004. Proceedings. 41st |
| Date Published | july |
| Abstract | Not available |
