Power/ground mesh area optimization using multigrid-based technique [IC design]

TitlePower/ground mesh area optimization using multigrid-based technique [IC design]
Publication TypeConference Paper
Year of Publication2003
AuthorsWang, K, Marek-Sadowska, M
Conference NameDesign, Automation and Test in Europe Conference and Exhibition, 2003
Keywordsback-mapping process, circuit optimisation, coarse mesh, integrated circuit design, integrated circuit reliability, large-scale mesh, logic design, mesh topology, multigrid-based technique, network topology, optimization speed increase, power/ground mesh area optimization, power/ground network synthesis, reliability constraints
AbstractIn this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to reduce a large-scale mesh to a much coarser one. The reduced mesh can be efficiently optimized. The solution for the original mesh is then computed using a back-mapping process. Experimental results are very encouraging. Large-scale power/ground meshes with millions of nodes can be solved in a few minutes. The proposed technique not only speeds up the optimization process significantly without compromising the quality of solutions, but also brings up the possibility of incorporating the power/ground mesh optimization into other physical design stages such as signal routing.