Buffer delay change in the presence of power and ground noise

TitleBuffer delay change in the presence of power and ground noise
Publication TypeJournal Article
Year of Publication2003
AuthorsChen, LH, Marek-Sadowska, M, Brewer, F
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Pagination461 -473
Date Publishedjune
Keywordsbuffer delay change, carrier velocity saturation, circuit optimisation, circuit performance optimization, closed-form formulas, delay models, delays, ground noise, integrated circuit noise, integrated circuit packaging, jitter characteristics, MOS integrated circuits, noise-on-signal propagation, packaging, repeater chains, short-channel MOSFET behavior, uncorrelated power noise, very large scale integration, VLSI
AbstractVariations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.