Minimizing inter-clock coupling jitter

TitleMinimizing inter-clock coupling jitter
Publication TypeConference Paper
Year of Publication2003
AuthorsHsiao, M-F, Marek-Sadowska, M, Chen, S-J
Conference NameQuality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Date Publishedmarch
Keywordschip performance, clock jitter, clock nets, clock topology, conventional clock tree synthesis, coupled circuits, crosstalk, Crosstalk noise, deep submicron technologies, integrated circuit noise, inter clock crosstalk, jitter, minimisation, minimizing inter clock coupling jitter, modern chip designs
AbstractCrosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and some-times even tens of them. It is therefore imperative to design clock topologies to prevent possible crosstalk among them. In this paper, we address the inter-clock crosstalk. We propose algorithms to design clock topology and to perform routing minimizing the effective crosstalk. Our experimental results show a significant reduction of clock jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock crosstalk effects.