| Title | PITIA: an FPGA for throughput-intensive applications |
| Publication Type | Journal Article |
| Year of Publication | 2003 |
| Authors | Singh, A, Mukherjee, A, Macchiarulo, L, Marek-Sadowska, M |
| Journal | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on |
| Volume | 11 |
| Pagination | 354 -363 |
| Date Published | june |
| ISSN | 1063-8210 |
| Keywords | 0.25 micron, 2.5 V, 625 MHz, clock network, CMOS logic circuits, CMOS technology, datapath circuit, deep submicron technology, field programmable gate array, field programmable gate arrays, pipelined interconnect, PITIA, power consumption, reconfigurable architecture, Rent exponent, routability, throughput-intensive design, wave steering |
| Abstract | In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625MHz in 0.25-/spl mu/m 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance. |
| DOI | 10.1109/TVLSI.2003.810780 |
