Minimizing coupling jitter by buffer resizing for coupled clock networks

TitleMinimizing coupling jitter by buffer resizing for coupled clock networks
Publication TypeConference Paper
Year of Publication2003
AuthorsHsiao, M-F, Marek-Sadowska, M, Chen, S-J
Conference NameCircuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Date Publishedmay
Keywordsbuffer resizing, buffered clock trees, chip performance, circuit CAD, clock jitter, clock nets, clocks, coupled clock networks, coupling effects, coupling jitter, deep submicron technologies, integrated circuit design, system performance, timing jitter, total area, VLSI
AbstractCrosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. It is therefore imperative to design clock buffers to reduce the coupling effects. In this paper, we address the crosstalk effect on clock networks. We propose an algorithm to size clock buffers for given buffered clock trees such that the induced clock jitter is minimized. Our experimental results show a significant reduction of clock jitter by sizing the clock buffers without increasing the total area of buffer.