Sizing power/ground meshes for clocking and computing circuit components

TitleSizing power/ground meshes for clocking and computing circuit components
Publication TypeConference Paper
Year of Publication2002
AuthorsMukherjee, A, Wang, K, Chen, LH, Marek-Sadowska, M
Conference NameDesign, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Keywordsbuffer delay change, circuit component delays, circuit optimisation, clock buffers, clocking components, datapath circuits, delays, ground mesh sizing problem, ground node potentials, integrated circuit layout, interconnected IP cores, linear programming, logic CAD, maximum IR-drop constraints, MCNC circuits, nonlinear programming, nonlinear programming problem, power dissipation, power drops, power sizing problem, power/ground IR-drops, sequence of linear programs solution, short-channel MOSFET model, synchronous circuits, timing, timing relations
AbstractThis paper presents a new formulation and an efficient solution of the power and ground mesh sizing problem. We use the key observations that (1) the drops in power and ground node potentials are due not only to currents drawn by the computing blocks, but also to those drawn by the clock buffers, and (2) changes of circuit component delays are linearly proportional to the power/ground IR-drops. This leads to a linear quantification of the timing relations between the clocking and computing components in terms of the power/ground IR-drops. Our method removes all IR-drop related timing violations that occur in about 2% of paths when grids are sized using the existing methods that satisfy the maximum IR-drop constraints. In addition, we achieve supply mesh area improvements of the order of 30% while simultaneously reducing the power dissipated in the circuits by about 6.6% compared to traditional grid sizing methods