Crosstalk minimization for multiple clock tree routing

TitleCrosstalk minimization for multiple clock tree routing
Publication TypeConference Paper
Year of Publication2002
AuthorsHsiao, M-F, Marek-Sadowska, M, Chen, S-J
Conference NameCircuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Date Publishedaug.
Keywordscircuit layout CAD, clock routing, clock topologies, clock topology, clocks, crosstalk, crosstalk minimization, deep submicron chip design, integrated circuit layout, integrated circuit noise, inter-clock crosstalk, minimisation of switching nets, multiple clock tree routing, network routing, noise sources, VLSI
AbstractCrosstalk noise has been identified as a very important factor for deep submicron chip design. Signals running in parallel on the same layer can experience crosstalk noise. Among all the possible crosstalk noise sources, clock is the most important aggressor as well as victim. Besides, for modern chip design, there is usually more than one clock source, sometimes tens of clock sources. It is important to design the clock topologies for all the clocks running on the same chip to prevent possible crosstalk noise among them. In this paper, we deal with the minimization of inter-clock crosstalk. We propose algorithms to generate clock topology and routing to minimize effective crosstalk. The experimental results show a significant reduction of effective crosstalk compared to that of the conventional clock tree synthesis wherein crosstalk effect is not taken into account.