Publications

Found 13 results
Filters: Author is Kwang-Ting Cheng  [Clear All Filters]
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S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., An efficient algorithm for local don't care sets calculation, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
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D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
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D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
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S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Layout Driven Logic Synthesis for FPGAs, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
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D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A new hybrid methodology for power estimation, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
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S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
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C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., Speeding up power estimation by topological analysis, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
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C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test point insertion: scan paths through combinational logic, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., A Test Synthesis Approach To Reducing Ballast Dft Overhead, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Test-point insertion: scan paths through functional logic, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.