Publications

Found 5 results
Filters: Author is Sao-Jie Chen  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
C
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
F
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
M
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.