Publications

Found 8 results
Filters: Author is Shen Lin  [Clear All Filters]
Conference Paper
S. Lin and Marek-Sadowska, M., An accurate and efficient delay model for CMOS gates in switch-level timing analysis, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., Delay and area optimization in standard-cell design, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
S. Lin and Marek-Sadowska, M., A fast and efficient algorithm for determining fanout trees in large networks, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., A New Accurate and Efficient Timing Simulator, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
M. Marek-Sadowska and Lin, S., Pin assignment for improved performance in standard cell design, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
M. Marek-Sadowska and Lin, S., Timing driven placement, in Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on, 1989, pp. 94 -97.
Journal Article
S. Lin, Kuh, E. S., and Marek-Sadowska, M., Stepwise equivalent conductance circuit simulation technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.