Found 231 results
W. Maly, Singh, N., Chen, Z., Shen, N., Li, X., Pfitzner, A., Kasprowicz, D., Kuzmicz, W., Yi-Wei Lin, and Marek-Sadowska, M., Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
Li, Di-an and Marek-Sadowska, M., Variation-aware electromigration analysis of power/ground networks, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
X. Qiu and Marek-Sadowska, M., Can pin access limit the footprint scaling?, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
F. Chen, Mittl, S., Shinosky, M., Swift, A., Kontra, R., Anderson, B., Aitken, J., Wang, Y., Kinser, E., Kumar, M., Wang, Y., Kane, T., Feng, K. D., Henson, W. K., Mocuta, D., and Li, Di-an, Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
V. S. Nandakumar and Marek-Sadowska, M., A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
X. Qiu, Marek-Sadowska, M., and Maly, W., Vertical Slit Field Effect Transistor in ultra-low power applications, in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 384 -390.