Publications

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Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., An Efficient Mechanism for Performance Optimization of Variable-Latency Designs, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., Performance Optimization Using Variable-Latency Design Style, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Interconnect pipelining in a throughput-intensive FPGA architecture, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Interconnect resource-aware placement for hierarchical FPGAs, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
A. Singh and Marek-Sadowska, M., Efficient circuit clustering for area and power reduction in FPGAs, in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, 2002, pp. 59–66.
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
A. Singh and Marek-Sadowska, M., FPGA interconnect planning, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
A. Singh and Marek-Sadowska, M., Circuit clustering using graph coloring, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., Efficient circuit clustering for area and power reduction in FPGAs, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
A. Singh, Macchiarulo, L., Mukherjee, A., and Marek-Sadowska, M., A novel high throughput reconfigurable FPGA architecture, in FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000, pp. 22–29.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Latency and latch count minimization in wave steered circuits, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.