Testing Analog Components in SoCs
Research Summary:
Analog components in system on chip designs (SoC) have proven to be very difficult to test within the digital design verification flow. These components are simulated and verified using SPICE, which can be very time consuming for more complex components. When targeting the behavior of the system it is critical that the analog components work as intended within the digital system. Unfortunately, current analog modeling techniques require expert knowledge and existing EDA tools cannot behaviorally model analog circuits working in conjunction with the digital components. We propose a machine learning method that will automatically create a behavioral System Verilog macromodel that removes the need for any SPICE simulation and can be tested using available EDA digital design tools.
Past Research:
Previous projects focused on improving the diagnostic resolution of timing defects modeled as transition faults. This included identifying structural and physical conditions that lead to un-diagnosable or un-distinguishable faults. Once the root cause of hard to detect faults is understood, it can be used to improve generation of diagnostic tests and to introduce incremental changes to the design to make it easier to diagnose. It is also possible to develop logic and physical design flow for diagnosability.
Papers/Posters:
Frequency Manipulation to Maximize the Diagnostic Resolution of Delay Faults
Authors: Samantha Alt (UC/Santa Barbara), Malgorzata Marek-Sadowska (UC/Santa Barbara), K-H. Tsai , J. Rajski
Techcon 10-Sep-2009
Abstract: It is important to accurately pinpoint a timing defect's location to minimize the time spent on failure analysis. To reduce the testing time, a compact test pattern set is commonly used, which may not be well suited for diagnosis. In this paper, the researchers propose a method that can increase the diagnostic resolution of the original minimum pattern set by properly adjusting the clock frequency. The algorithm utilizes candidate fault locations and passing pattern information to select the new clock period. Their intention is to observe unresolved fault candidates that propagate through properly selected paths. They use the estimated delay fault size that, in addition to the path delay, will produce a new clock period for diagnosis. Under the single fault assumption, their method can obtain an optimal diagnostic resolution for the original compact pattern set.
Research Summary:
Analog components in system on chip designs (SoC) have proven to be very difficult to test within the digital design verification flow. These components are simulated and verified using SPICE, which can be very time consuming for more complex components. When targeting the behavior of the system it is critical that the analog components work as intended within the digital system. Unfortunately, current analog modeling techniques require expert knowledge and existing EDA tools cannot behaviorally model analog circuits working in conjunction with the digital components. We propose a machine learning method that will automatically create a behavioral System Verilog macromodel that removes the need for any SPICE simulation and can be tested using available EDA digital design tools.
Past Research:
Previous projects focused on improving the diagnostic resolution of timing defects modeled as transition faults. This included identifying structural and physical conditions that lead to un-diagnosable or un-distinguishable faults. Once the root cause of hard to detect faults is understood, it can be used to improve generation of diagnostic tests and to introduce incremental changes to the design to make it easier to diagnose. It is also possible to develop logic and physical design flow for diagnosability.
Papers/Posters:
Frequency Manipulation to Maximize the Diagnostic Resolution of Delay Faults
Authors: Samantha Alt (UC/Santa Barbara), Malgorzata Marek-Sadowska (UC/Santa Barbara), K-H. Tsai , J. Rajski
Techcon 10-Sep-2009
Abstract: It is important to accurately pinpoint a timing defect's location to minimize the time spent on failure analysis. To reduce the testing time, a compact test pattern set is commonly used, which may not be well suited for diagnosis. In this paper, the researchers propose a method that can increase the diagnostic resolution of the original minimum pattern set by properly adjusting the clock frequency. The algorithm utilizes candidate fault locations and passing pattern information to select the new clock period. Their intention is to observe unresolved fault candidates that propagate through properly selected paths. They use the estimated delay fault size that, in addition to the path delay, will produce a new clock period for diagnosis. Under the single fault assumption, their method can obtain an optimal diagnostic resolution for the original compact pattern set.
