- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publications
, “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
, “mFAR: fixed-points-addition-based VLSI placement algorithm”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
, “Decomposition of multiple-valued relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
