- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publications
, “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
, “A novel high throughput reconfigurable FPGA architecture”, in FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000, pp. 22–29.
, “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
