Publications

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A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
V. S. Nandakumar and Marek-Sadowska, M., “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Tsai and Marek-Sadowska, M., “Logic synthesis for testability”, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
V. S. Nandakumar and Marek-Sadowska, M., “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
V. S. Nandakumar and Marek-Sadowska, M., “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
A. Vittal and Marek-Sadowska, M., “Low-power buffered clock tree design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.