Publications

Found 9 results
Filters: Author is Chih-Wei Chang  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
C
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
C. - W. Chang and Marek-Sadowska, M., “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
C. - W. Chang, Hu, B., and Marek-Sadowska, M., “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
C. - W. Chang and Marek-Sadowska, M., “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., “Fast post-placement rewiring using easily detectable functional symmetries”, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
C. - W. Chang and Marek-Sadowska, M., “Theory of wire addition and removal in combinational Boolean networks”, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
C. - W. Chang and Marek-Sadowska, M., “Who are the alternative wires in your neighborhood? (alternative wires identification without search)”, in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.