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K. Wang and Marek-Sadowska, M., “On-chip power-supply network optimization using multigrid-based technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
K. Wang and Marek-Sadowska, M., “Buffer sizing for clock power minimization subject to general skew constraints”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
K. Wang and Marek-Sadowska, M., “Potential slack budgeting with clock skew optimization”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
K. Wang and Marek-Sadowska, M., “Power/ground mesh area optimization using multigrid-based technique [IC design]”, in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
K. Wang and Marek-Sadowska, M., “On-chip power supply network optimization using multigrid-based technique”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
K. Wang and Marek-Sadowska, M., “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.