Publications

Found 9 results
Filters: Keyword is integrated circuit testing  [Clear All Filters]
2008
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
2006
V. Mehta, Wang, Z., Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis for nonrobust test”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -472.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology”, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
2003
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
2000
T. Xiao, Chang, C. - W., and Marek-Sadowska, M., “Efficient static timing analysis in presence of crosstalk”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 335 -339.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
1998
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
1997
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
1996
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.