Publications

Found 266 results
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Journal Article
C. - Y. Yeh and Marek-Sadowska, M., “Sequential delay budgeting with interconnect prediction”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
M. Marek-Sadowska and Tarng, T. T. - K., “Single-Layer Routing for VLSI: Analysis and Algorithms”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
Q. Liu and Marek-Sadowska, M., “A study of netlist structure and placement efficiency”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.
M. Marek-Sadowska, “Switch box routing: a retrospective”, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
C. - W. Chang and Marek-Sadowska, M., “Theory of wire addition and removal in combinational Boolean networks”, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
C. - Y. Yeh and Merek-Sadowska, M., “Timing-Aware Power-Noise Reduction in Placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 527 -541, 2007.
M. Marek-Sadowska, “An Unconstrained Topological Via Minimization Problem for Two-Layer Routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 184 - 190, 1984.
Y. Ran and Marek-Sadowska, M., “Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 998 -1009, 2006.
A. Mukherjee and Marek-Sadowska, M., “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
A. Mukherjee and Marek-Sadowska, M., “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.

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