Publications

Found 14 results
Filters: Author is Bo Hu  [Clear All Filters]
2001
C. - W. Chang, Hu, B., and Marek-Sadowska, M., In-place delay constrained power optimization using functional symmetries, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
2002
B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
B. Hu and Marek-Sadowska, M., FAR: fixed-points addition & relaxation based placement, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
2003
B. Hu and Marek-Sadowska, M., Fine granularity clustering for large scale placement problems, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
B. Hu, Watanabe, Y., and Marek-Sadowska, M., Gain-based technology mapping for discrete-size cell libraries, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
B. Hu and Marek-Sadowska, M., Wire length prediction based clustering and its application in placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
Q. Liu, Hu, B., and Marek-Sadowska, M., Wire length prediction in constraint driven placement, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
2004
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
B. Hu and Marek-Sadowska, M., Fine granularity clustering-based placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
Q. Liu, Hu, B., and Marek-Sadowska, M., Individual wire-length prediction with application to timing-driven placement, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
B. Hu and Marek-Sadowska, M., Multilevel expansion-based VLSI placement with blockages, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
2005
B. Hu, Zeng, Y., and Marek-Sadowska, M., mFAR: fixed-points-addition-based VLSI placement algorithm, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
B. Hu and Marek-Sadowska, M., Multilevel fixed-point-addition-based VLSI placement, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.