Publications

Found 13 results
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2011
J. - Y. Wuu, Pikus, F. G., Marek-Sadowska, M., and Rieger, M. L., “Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching”, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Metrics for characterizing machine learning-based hotspot detection methods”, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, pp. 1 -6.
J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
W. Maly, Singh, N., Chen, Z., Shen, N., Li, X., Pfitzner, A., Kasprowicz, D., Kuzmicz, W., Yi-Wei Lin, and Marek-Sadowska, M., “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
2009
J. - Y. Wuu, Pikus, F. G., Torres, A., Marek-Sadowska, M., Singh, V. K., and Rieger, M. L., “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
2008
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Fast and simple modeling of non-rectangular transistors”, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
2002
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Efficient circuit clustering for area and power reduction in FPGAs”, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
2001
G. Parthasarathy, Marek-Sadowska, M., Mukherjee, A., and Singh, A., “Interconnect complexity-aware FPGA placement using Rent's rule”, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
1997
S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., “Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
M. Perkowski, Marek-Sadowska, M., Jozwiak, L., Luba, T., Grygiel, S., Nowicka, M., Malvi, R., Wang, Z., and Zhang, J. S., “Decomposition of multiple-valued relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
1990
M. Pedram, Marek-Sadowska, M., and Kuh, E. S., “Floorplanning with pin assignment”, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.