Publications
, “An interconnect insensitive linear time-varying driver model for static timing analysis”, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
, “Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms”, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
, “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
, “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
, “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
, “Analysis of process variation's effect on SRAM's read stability”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
, “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
, “Starbist Scan Autocorrelated Random Pattern Generation”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
, “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
, “Modeling crosstalk induced delay”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
, “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
, “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
, “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
, “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
, “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
, “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
, “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
, “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
, “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
, “Electromigration and voltage drop aware power grid optimization for power gated ICs”, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
, “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
, “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
, “An Efficient Mechanism for Performance Optimization of Variable-Latency Designs”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
, “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
, “Interconnect pipelining in a throughput-intensive FPGA architecture”, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
