Publications

Found 266 results
Filters: First Letter Of Last Name is M  [Clear All Filters]
1995
A. Vittal and Marek-Sadowska, M., “Power Optimal Buffered Clock Tree Design”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
Y. - L. Wu and Marek-Sadowska, M., “Routing on regular segmented 2-D FPGAs”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 329 -334.
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
1994
C. - C. Tsai and Marek-Sadowska, M., “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
C. - C. Tsai and Marek-Sadowska, M., “Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms”, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
Y. - L. Wu and Marek-Sadowska, M., “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
A. Vittal and Marek-Sadowska, M., “Minimal Delay Interconnect Design Using Alphabetic Trees”, in Design Automation, 1994. 31st Conference on, 1994, pp. 392 - 396.
C. - C. Tsai and Marek-Sadowska, M., “Minimisation of fixed-polarity AND/XOR canonical networks”, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
S. - C. Chang and Marek-Sadowska, M., “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
C. - C. Lin, Marek-Sadowska, M., and Gatlin, D., “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
1993
C. - C. Tsai and Marek-Sadowska, M., “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
Y. - L. Wu and Marek-Sadowska, M., “Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu and Marek-Sadowska, M., “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
S. - C. Chang and Marek-Sadowska, M., “Technology mapping and circuit depth optimization for field programmable gate arrays”, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
D. I. Cheng and Marek-Sadowska, M., “Verifying equivalence of functions with unknown input correspondence”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
1992
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
M. Marek-Sadowska, “Switch box routing: a retrospective”, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
S. - C. Chang and Marek-Sadowska, M., “Technology mapping via transformations of function graphs”, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
B. Chen and Marek-Sadowska, M., “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
1991
M. Marek-Sadowska and Sarrafzadeh, M., “The crossing distribution problem”, in Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, 1991, pp. 528 -531.
S. Lin and Marek-Sadowska, M., “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.

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