Publications

Found 228 results
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1983
M. Marek-Sadowska and Kuh, E. S., “General channel-routing algorithm”, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
M. Marek-Sadowska and Tarng, T. T. - K., “Single-Layer Routing for VLSI: Analysis and Algorithms”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.
1984
T. T. - K. Tarng, Marek-Sadowska, M., and Kuh, E. S., “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
J. - T. Li and Marek-Sadowska, M., “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
M. Marek-Sadowska, “An Unconstrained Topological Via Minimization Problem for Two-Layer Routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 184 - 190, 1984.
1985
M. Marek-Sadowska, “Two-Dimensional Router for Double Layer Layout”, in Design Automation, 1985. 22nd Conference on, 1985, pp. 117 - 123.
1987
M. Marek-Sadowska, “Pad Assignment for Power Nets in VLSI Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 550 - 560, 1987.
1989
F. Makedon and Marek-Sadowska, M., “Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic”, in ICCAL '89: Proceedings of the 2nd International Conference on Computer Assisted Learning, 1989, pp. 359–378.
R. Dutta and Marek-Sadowska, M., “Automatic Sizing of Power/Ground (P/G) Networks in VLSI”, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.
M. Marek-Sadowska and Lin, S., “Timing driven placement”, in Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on, 1989, pp. 94 -97.
1990
S. Lin and Marek-Sadowska, M., “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
M. Pedram, Marek-Sadowska, M., and Kuh, E. S., “Floorplanning with pin assignment”, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.
M. Marek-Sadowska and Lin, S., “Pin assignment for improved performance in standard cell design”, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
1991
M. Marek-Sadowska and Sarrafzadeh, M., “The crossing distribution problem”, in Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, 1991, pp. 528 -531.
S. Lin and Marek-Sadowska, M., “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
1992
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
M. Marek-Sadowska, “Switch box routing: a retrospective”, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
S. - C. Chang and Marek-Sadowska, M., “Technology mapping via transformations of function graphs”, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
B. Chen and Marek-Sadowska, M., “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
1993
C. - C. Tsai and Marek-Sadowska, M., “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
Y. - L. Wu and Marek-Sadowska, M., “Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu and Marek-Sadowska, M., “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.

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