Publications
“Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
, “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
, “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
, “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
, “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
, “Power-Gating Aware Floorplanning”, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
, “Power/Ground Supply Network Optimization for Power-Gating”, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
, “Pre-layout physical connectivity prediction with application in clustering-based placement”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
, “Pipelining sequential circuits with wave steering”, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
, “Potential slack budgeting with clock skew optimization”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
, “Pre-layout wire length and congestion estimation”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
, “PITIA: an FPGA for throughput-intensive applications”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
, “Power/ground mesh area optimization using multigrid-based technique [IC design]”, in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
, “Partitioning sequential circuits on dynamically reconfigurable FPGAs”, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
, “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
, “Postlayout logic restructuring using alternative wires”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
, “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
, “Perturb and simplify: optimizing circuits with external don't cares”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
, “Power Distribution Topology Design”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
, “Power Optimal Buffered Clock Tree Design”, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
, “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
, “Pin assignment for improved performance in standard cell design”, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
, “Pad Assignment for Power Nets in VLSI Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 550 - 560, 1987.
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