Publications

Found 23 results
Filters: First Letter Of Title is P  [Clear All Filters]
2011
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., Performance Optimization Using Variable-Latency Design Style, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
A. Todri and Marek-Sadowska, M., Power Delivery for Multicore Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
2010
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Performance study of VeSFET-based, high-density regular circuits, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
2008
H. Jiang and Marek-Sadowska, M., Power gating scheduling for power/ground noise reduction, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., Power supply noise aware workload assignment for multi-core systems, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
2007
H. Jiang and Marek-Sadowska, M., Power-Gating Aware Floorplanning, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
2006
H. Jiang and Marek-Sadowska, M., Power/Ground Supply Network Optimization for Power-Gating, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
2005
Q. Liu and Marek-Sadowska, M., Pre-layout physical connectivity prediction with application in clustering-based placement, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
2004
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Pipelining sequential circuits with wave steering, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
Q. Liu and Marek-Sadowska, M., Pre-layout wire length and congestion estimation, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
2003
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
1999
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
1997
Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
1996
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
1995
A. Vittal and Marek-Sadowska, M., Power Distribution Topology Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
A. Vittal and Marek-Sadowska, M., Power Optimal Buffered Clock Tree Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
1994
S. - C. Chang and Marek-Sadowska, M., Perturb And Simplify: Multi-level Boolean Network Optimizer, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
1990
M. Marek-Sadowska and Lin, S., Pin assignment for improved performance in standard cell design, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
1987
M. Marek-Sadowska, Pad Assignment for Power Nets in VLSI Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 550 - 560, 1987.