Publications

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Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Multiple fault diagnosis using n-detection tests”, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
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Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
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A. Todri and Marek-Sadowska, M., “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
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J. - Y. Wuu, Pikus, F. G., Torres, A., and Marek-Sadowska, M., “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
A. Todri and Marek-Sadowska, M., “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
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K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
M. Marek-Sadowska and Tarng, T. T. - K., “Single-Layer Routing for VLSI: Analysis and Algorithms”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., “Starbist Scan Autocorrelated Random Pattern Generation”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
A. Todri and Marek-Sadowska, M., “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
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D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology”, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.

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