Publications

Found 231 results
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C. - C. Tsai and Marek-Sadowska, M., Logic synthesis for testability, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
C. - C. Tsai and Marek-Sadowska, M., Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Scan encoded test pattern generation for BIST, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
C. - K. Tsai and Marek-Sadowska, M., Analysis of process variation's effect on SRAM's read stability, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., Starbist Scan Autocorrelated Random Pattern Generation, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
C. - C. Tsai and Marek-Sadowska, M., Boolean Matching Using Generalized Reed-Muller Forms, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
C. - K. Tsai and Marek-Sadowska, M., Modeling crosstalk induced delay, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
C. - C. Tsai and Marek-Sadowska, M., Efficient minimization algorithms for fixed polarity AND/XOR canonical networks, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Star test: the theory and its applications, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., STAR-ATPG: a high speed test pattern generator for large scan designs, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
C. - C. Tsai and Marek-Sadowska, M., Multilevel logic synthesis for arithmetic functions, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
A. Todri, Marek-Sadowska, M., and Chang, S. - C., Analysis and optimization of power-gated ICs with multiple power gating configurations, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
A. Todri and Marek-Sadowska, M., Power Delivery for Multicore Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., Power supply noise aware workload assignment for multi-core systems, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
A. Todri and Marek-Sadowska, M., A study of reliability issues in clock distribution networks, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., A study of decoupling capacitor effectiveness in power and ground grid networks, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
A. Todri and Marek-Sadowska, M., Electromigration study of power-gated grids, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
A. Todri, Chang, S. - C., and Marek-Sadowska, M., Electromigration and voltage drop aware power grid optimization for power gated ICs, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
A. Todri and Marek-Sadowska, M., Reliability Analysis and Optimization of Power-Gated ICs, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
T. T. - K. Tarng, Marek-Sadowska, M., and Kuh, E. S., An Efficient Single-Row Routing Algorithm, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
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Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., An Efficient Mechanism for Performance Optimization of Variable-Latency Designs, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., Performance Optimization Using Variable-Latency Design Style, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., Interconnect pipelining in a throughput-intensive FPGA architecture, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.

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