Publications
, “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
, “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
, “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
, “Interconnect pipelining in a throughput-intensive FPGA architecture”, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
, “An interconnect insensitive linear time-varying driver model for static timing analysis”, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
, “Interconnect complexity-aware FPGA placement using Rent's rule”, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
, “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
, “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
, “Incremental delay change due to crosstalk noise”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 120–125.
, “Graph based analysis of FPGA routing”, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
, “A global routing technique for wave-steered design methodology”, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
, “Gate sizing to eliminate crosstalk induced timing violation”, in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 186 -191.
, “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
, “Functional scan chain testing”, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
, “Functional correlation analysis in crosstalk induced critical paths identification”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.
, “FPGA interconnect planning”, in SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, 2002, pp. 23–30.
, “Floorplanning with pin assignment”, in Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on, 1990, pp. 98 -101.
, “Fine granularity clustering for large scale placement problems”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
, “Fast post-placement rewiring using easily detectable functional symmetries”, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “Fast and simple modeling of non-rectangular transistors”, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
, “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
, “FAR: fixed-points addition & relaxation based placement”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
